1. Technical Field
The present invention relates to a semiconductor device.
2. Description of the Related Art
Semiconductor integrated circuits, particularly integrated circuits using MOS transistors, are increasing in integration. With increases in integration, MOS transistors used in the integrated circuits increasingly become finer up to a nano-level. Such finer MOS transistors have difficulty in suppressing leak currents and difficulty in decreasing areas occupied by circuits in view of the demand for securing necessary amounts of currents. In order to resolve the problem, there are proposed surrounding gate transistors (referred to as “SGT” hereinafter) having a structure in which a source, gate, and drain are disposed perpendicularly to a substrate, and a gate electrode surrounds a pillar-shaped semiconductor layer (for example, refer to Japanese Unexamined Patent Application Publication Nos. 2-715562, 2-188966, and 3-145761).
A conventional SGT manufacturing method includes forming a silicon pillar having a pillar-shaped nitride film hard mask formed thereon, forming a diffusion layer in a lower portion of the silicon pillar, depositing a gate material, planarizing the gate material, etching back the gate material, and forming an insulating film sidewall on sidewalls of the silicon pillar and the nitride film hard mask. Then, a resist pattern for a gate line is formed, the gate material is etched, the nitride film hard mask is removed, and a diffusion layer is formed in an upper portion of the silicon pillar (for example, refer to Japanese Unexamined Patent Application Publication No. 2009-182317). Then, a nitride film sidewall is formed on the sidewall of the silicon pillar, a diffusion layer is formed in an upper portion of the silicon pillar by ion implantation, a nitride film is formed as a contact stopper, an oxide film is formed as an interlayer film, and then contact etching is performed.
It is known that oxide film etching for forming a contact has a high selection ratio to a nitride film in a flat portion, but the selection ratio in a nitride film shoulder portion is lower than that in the flat portion.
Since the diameter of a silicon pillar of SGT decreases with reduction in size, a flat area is decreased. In addition, a nitride film sidewall corresponds to a nitride film shoulder portion, and thus the selection ratio of etching an oxide film is decreased. Therefore, etching an oxide film to form a contact on a silicon pillar is not stopped by a nitride film to form a contact hole which reaches a gate, resulting in short-circuiting between the silicon pillar and the gate.
There is proposed a structure for preventing the occurrence of short-circuiting between a contact and a gate by forming an epitaxial semiconductor layer on a silicon pillar of SGT (refer to, for example, Japanese Unexamined Patent Application Publication No. 2010-258345). However, epitaxial growth requires insulating film sidewalls to be formed on an upper sidewall of the silicon pillar and on an upper portion of a gate electrode. When polysilicon is used in a gate, silicon is also grown on the gate. Therefore, epitaxial growth to a height equal to or higher than the height of the insulating film sidewall causes short-circuiting between the gate and an upper portion of the silicon pillar.
On the other hand, the nitride film sidewall is formed on the sidewall of the silicon pillar, and the diffusion layer is formed in an upper portion of the silicon pillar by ion implantation. Therefore, ions are implanted from above into an upper portion of the silicon pillar, and thus a deep diffusion layer is required to be formed. When a deep diffusion layer is formed, the diffusion layer is also widened in the lateral direction. That is, higher integration becomes difficult to achieve.
In addition, when the silicon pillar becomes thin, it is difficult to allow impurities to present in the silicon pillar because the silicon density is 5×1022/cm3.
It is described that in a flat-type MOS transistor, a sidewall of a LDD region is composed of polycrystal silicon having the same conductivity type as a low-concentration layer, and surface carriers of the LDD region are induced by a difference in work function, thereby decreasing the impedance of the LDD region as compared an oxide film sidewall LDD-type MOS transistor (refer to, for example, Japanese Unexamined Patent Application Publication No. 11-297984). It is also described that the polycrystal silicon sidewall is electrically insulated from the gate electrode. Also, drawings show that the polycrystal silicon sidewall is insulated from source/drain through an interlayer insulating film.